Inherent thin film properties of materials can limit many surface micromachining processes. For example, variability of materials properties in polysilicon thin films can prohibit the manufacture of desired microstructures. This is particularly apparent in micro-optical components, such as mirrors, lenses, diffraction gratings, and micro-electromechanical structures (MEMS).
The leading commercial MEMS processing technologies are bulk micromachining of single crystal silicon, and surface micromachining of polycrystalline silicon. Each of these processing technologies has associated benefits and barriers. Single crystal silicon bulk micromachining is a material with well-controlled electrical and mechanical properties in its pure state. Single crystal silicon bulk micromachining has historically utilized wet anisotropic and wet etching to form mechanical elements. In this process, the etch rate is dependent on the crystallographic planes that are exposed to the etch solution, so that mechanical elements are formed that are aligned to the rate limiting crystallographic planes. The etch rate also varies with dopant concentration, so that the etch rate can be modified by the incorporation of dopant atoms, which substitute for silicon atoms in the crystal lattice.
In contrast to bulk micromachining, surface micromachining of polycrystalline silicon can utilize chemical vapor deposition (CVD) and reactive ion etching (RIE) patterning techniques to form mechanical elements from stacked layers of thin films (see, e.g., R. T. Howe, “Surface micromachining for microsensors and microactuators”, J. Vac. Sci. Technol. B6, (1988) 1809). Typically, CVD polysilicon is used to form the mechanical elements, CVD nitride is used to form electrical insulators, and CVD oxide is used as a sacrificial layer. Removal of the oxide by wet or dry etching releases the polysilicon thin film structures. The advantage of the surface micromachining process is the ability to make complex structures in the direction normal to the wafer surface by stacking releasable polysilicon layers (see, for example, K. S. J. Pister, M. W. Judy, S. R. Burgett, and R. S. Fearing, “Microfabricated hinges”, Sensors and Actuators A33, (1992) 249; and L. Y. Lin, S. S. Lee, K. S. J. Pister, and M. C. Wu, “Micromachined three-dimensional micro-optics for free-space optical system”, IEEE Photon. Technol. Lett. 6, (1994) 1445) and complete geometric design freedom in the plane of the wafer since the device layers are patterned using isotropic RIE etching techniques.
While surface micromachining relaxes many of the limitations inherent in bulk micromachining of single crystal silicon, it nonetheless has its own limitations in thin film properties. For example, the maximum film thickness that can be deposited from CVD techniques is limited to several microns, so that thicker structures must be built up from sequential depositions.
An integrated MEMS printhead generally consists of two wafers, a MEMS transducer array and an electronics driver/control element. The printhead is formed by bonding these two wafers together. Traditional approaches require etching deep cavities into one of the silicon wafers, thus reducing available surface area for functional use. Other approaches can require complex, high stress features to be built up from the surface. These structures are typically metals, such as, for example, nickel that require plating chemistries that are incompatible with CMOS processing. The metal stack not only forms the ink chambers, but also allows for electrical vias between the two wafers.